1. Field of the Invention
This invention relates to the minimizing of timing errors in electronic circuits and particularly to improving the performance of comparator circuits used when converting an arbitrary wave shape to a binary waveform.
2. Description of the Prior Art
Comparator circuits normally exhibit significant differences in time delay when switching, dependent on whether the output is transversing high to low or low to high, associated with the turn on and turn off delays of the output device. These delays are determined by different electrical mechanisms and hence also vary differently with temperature.
FIG. 4 shows a conventional comparator, identifying the input signals V.sub.1 and V.sub.2 and the output signal V.sub.3, and FIG. 5 shows the signals associated with the comparator in FIG. 4.
A conventional comparator circuit will exhibit a time delay between when V.sub.1 exceeds V.sub.2 and the output voltage V.sub.3 starting to change (rise), say t.sub.1, further there will be a finite time between the output voltage starting to change and when it has finished changing, say t.sub.2.
There will be another time delay between V.sub.1 falling below V.sub.2 & V.sub.3 starting to fall, say t.sub.3 and a further finite time between when V.sub.3 starts to fall and has finished changing, say t.sub.4. Normally t.sub.1 does not equal t.sub.3, neither does t.sub.2 equal t.sub.4 nor does (t.sub.1 +t.sub.2)-(t.sub.3 +t.sub.4); further t.sub.1,t.sub.2,t.sub.3 and t.sub.4 will all change as the temperature varies and by differing amounts as they are determined by different mechanisms.
One effect of these differing time delays is to make it appear that the comparator has different reference voltages for positive going inputs and negative going inputs (akin to hysteresis and further that these references vary with temperature. Using high speed devices can reduce the effect at the expense of large increases in power.